Master-Level Verilog Assignment Solved

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Assignment: Design a 4-bit synchronous up/down counter in Verilog with asynchronous reset and enable.

Solution :

module counter(input clk, reset, enable, up_down, output reg [3] count);
always @(posedge clk or posedge reset)
if (reset) count <= 0;
else if (enable)
count <= up_down ? count + 1 : count - 1;
endmodule
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Solution (Expert Sample):
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